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This is a research and Innovation Action of the Eu Horizon 2020 Programme


Starting date: 1/1/2016; duration: 42 months


Objectives: We propose to fabricate a chip implementing a neuromorphic architecture that supports state-of-the-art machine learning and spike-based learning mechanisms. With respect to its physical architecture this chip will feature an ultra low power, scalable and highly configurable neural architecture that will deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions; and a monolithically integrated 3D technology in Fully-Depleted Silicon on Insulator (FDSOI) at 28nm design rules with integrated Resistive Random Access Memory (RRAM) synaptic elements; We will complete this vision and develop complementary technologies that will allow to address the full spectrum of applications from mobile/autonomous objects to high performance computing coprocessing, by realizing: (1) a technology to implement on-chip learning, using native adaptive characteristics of electronic synaptic elements; and (2) a scalable platform to interconnect multiple neuromorphic processor chips to build large neural processing systems. The neuromorphic computing system will be developed jointly with advanced neural algorithms and computational architectures for online adaptation, learning, and high-throughput on-line signal processing, delivering - an ultra-low power massively parallel non von Neumann computing platform with non-volatile nano-scale devices that support on-line learning mechanisms - a programming toolbox of algorithms and data structures tailored to the specific constraints and opportunities of the physical architecture; - an array of fundamental application demonstrations instantiating the basic classes of signal processing tasks. The neural chip will validate the concept and be a first step to develop a European technology platform addressing from ultra-low power data processing in autonomous systems (Internet of Things) to energy efficient large data processing in servers and networks.

CNR Principal Investigator: Sabina Spiga

Published article on CNR-Almanacco della Scienza (in Italian):"In arrivo il chip neuromorfico"

Workshop organized by NeuRAM3: "Technology and architectures development for Brain Inspired Integrated Circuits"

Press Release:


EE News logo Experimenting with neural architectures in silicon

EE Times logo AI’s Limits Send Scientists Back to the Brain

Recent Publications:

-   S. Brivio, J. Frascaroli, E. Covi and S. Spiga , "Stimulated Ionic Telegraph Noise in Filamentary Memristive Devices", Scientific Reports 9, 6310 (2019)

- S. Brivio, D. Conti, M. V. Nair, J. Frascaroli, E. Covi, C. Ricciardi, G. Indiveri and S. Spiga, "Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics", Nanotechnology 30, 015102 (2019)

- J. Frascaroli, S. Brivio, E. Covi, and  S. Spiga, "Evidence of soft bound behaviour in analogue memristive devices for neuromorphic computing", Scientific Reports Vol. 8, 7178 (2018)

E. Covi, R. George, J. Frascaroli, S. Brivio, C. Mayr, H. Mostafa, G. Indiveri and S. Spiga, "Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons", Journal of Physics D: Applied Physics Vol. 51 Page 344003 (2018)

 - S. Brivio, J. Frascaroli, and S. Spiga, "Role of Al doping in the filament disruption in HfO2 resistance switches", Nanotechnology Vol. 28 Page 395202 (2017)

- S. Brivio and S. Spiga, "Stochastic circuit breaker network model for bipolar resistance switching memories", Journal of Computation Electronics Vol. 16 Page 1154 (2017)

- H.-Yu Chen, S. Brivio, C.-C. Chang, J. Frascaroli, T.-H. Hou, B. Hudec, M. Liu, H. Lv, G. Molas, J. Sohn, S. Spiga, V. M. Teja, E. Vianello, H.-S. P.p Wong, Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication, J Electroceramics, Volume 39, Issue 1–4, pp 21–38 (2017)








2016-01-01 to 2019-06-30