This paper reviews the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the nowadays generalized scaling scenario. The capabilities to describe devices with arbitrary crystal orientations and strain configurations are discussed. Several simulation results are illustrated and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities of the models. A case study concerning the drain currents in nano-scale uniaxially strained MOSFETs is presented and it shows how the strain engineering may change the traditional on-current disadvantage of the p-MOS compared to the n-MOS transistors.
1 Oct 2009
Volume: 8 Issue: 3-4 Pages: 209
Journal of computational electronics